1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a more accurate method for forming an ultra-small gate conductor of an MOS transistor.
2. Description of the Related Art
Fabrication of a metal-oxide semiconductor ("MOS") transistor is well known. The manufacture of an MOS transistor begins by defining active areas where the transistor will be formed. The active areas are isolated from other areas on the semiconductor substrate by various isolation structures formed upon and within the substrate. Isolation structures come in many forms. For example, the isolation structures can be formed by etching trenches into the substrate and then filling the trenches with a dielectric fill material. Isolation structures may also be formed by locally oxidizing the silicon substrate using the well recognized LOCOS technique.
Once the isolation structures are defined between transistor active areas, a gate dielectric is formed. Typically, the gate dielectric is formed by thermal oxidation of the silicon substrate. Thermal oxidation is achieved by subjecting the substrate to an oxygen-bearing, heated ambient in, for example, an oxidation furnace or a rapid thermal annealer ("RTA"). A gate conductor material is then deposited across the entire dielectric-covered substrate. The gate conductor material is preferably polycrystalline silicon, or polysilicon. The polysilicon layer is then patterned using a photolithography mask. The mask allows select removal of a light-sensitive material deposited entirely across polysilicon. The material which is exposed can, according to one embodiment, be polymerized, and that which is not exposed removed. Selective polymerization is often referred to as the "develop" stage of lithography. The regions which are non-polymerized are removed using the etch stage of lithography.
Conventional lithography used to pattern a gate conductor suffers many drawbacks. For example, selective exposure is highly dependent upon accurately placing light on the light-sensitive material. Furthermore, the light-sensitive material must consistently respond to the light with fine-line resolution. Any elevational disparity on which the polysilicon resides will result in slight changes in the point at which light impinges on the light-sensitive material. This results in a variation of the polymerized/non-polymerized boundary.
It would be advantageous to form a gate conductor without having to rely upon conventional patterning techniques. The impetus behind wanting to change gate formation methodology is principally driven from the smaller gate sizes of modern day integrated circuits. As gate lengths and widths become smaller to accommodate higher density circuits, it is necessary that the relatively small gate conductors be accurately produced with minimal misalignment or size variation. Any changes in the placement and geometry of a gate conductor can have negative performance effects on the ensuing MOS transistor.
An n-channel transistor, or NMOS transistor, must in most instances be fabricated different from a p-channel transistor, or PMOS transistor. NMOS transistors employ n-type dopants on opposite sides of the NMOS gate conductor, whereas PMOS transistors employ p-type dopants on opposite sides of the PMOS transistor gate conductor. The regions of the substrate which receive dopants on opposite sides of the gate conductor are generally referred to as junction regions, and the distance between junction regions is typically referred to as the physical channel length. After implantation and subsequent diffusion of the junction regions, the distance between the junction regions becomes less than the physical channel length and is often referred to as the effective channel length ("Leff"). In high density designs, not only does the physical channel length become small so too must the Leff. As Leff decreases below approximately 1.0 .mu.m, for example, a problem known as short channel effects ("SCE") becomes predominant.
Generally speaking, SCE impacts device operation by, inter alia, reducing device threshold voltages and increasing sub-threshold currents. As Leff becomes small enough, the depletion regions associated with the junction areas may extend toward one another and substantially occupy the channel area. Hence, some of the channel will be partially depleted without any influence of gate voltage. Even at times when the gate voltage is below the threshold amount, current between the junctions (often referred to as subthreshold current) nonetheless exists for transistors having a relatively short Leff.
A problem related to SCE, and the subthreshold currents associated therewith, but altogether different is the problem of hot-carrier effects ("HCE"). HCE is a phenomenon by which hot-carriers ("holes and electrons") arrive at or near an electric field gradient. The electric field gradient, often referred to as the maximum electric field ("Em") occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent to the channel. The electric field at the drain causes primarily electrons in the channel to gain kinetic energy and become "hot". These hot electrons traveling to the drain lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge accumulates with time, resulting in a positive threshold shift in the NMOS transistor, or a negative threshold shift in a PMOS transistor. It is known that since hot electrons are more mobile than hot holes, HCE causes a greater threshold skew in NMOS transistors than PMOS transistors. Nonetheless, a PMOS transistor will undergo negative threshold skew if its Leff is less than, e.g., 0.8 .mu.m.
Unless modifications are made to the process in which relatively small transistors are formed, problems with sub-threshold current and threshold shift resulting from SCE and HCE will remain. To overcome these problems, alternative drain structures such as double-diffused drains ("DDD") and lightly doped drains ("LDD") must be used. The purpose of both types of structures is the same: to absorb some of the potential into the drain and thus reduce Em. The popularity of DDD structures has given way to LDD structures since DDD causes unacceptably deep junctions and deleterious junction capacitance.
A conventional LDD structure is one whereby a light concentration of dopant is self-aligned to the edge of the gate conductor. The light-dopant concentration is then followed by a heavier-dopant concentration which is self-aligned to a spacer formed on the sidewalls of the gate conductor. The purpose of the first implant dose is to produce a lightly doped section of both the source and drain junction areas at the gate edge near the channel. The second implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacer. Resulting from the first and second implants, a dopant gradient occurs across the junction from the source/drain area of the junction to the LDD area adjacent the channel.
A properly defined LDD implant area must be one which minimizes HCE but not at the expense of excessive source/drain resistance. The addition of an LDD implant adjacent the channel unfortunately adds resistance to the source/drain path. This added resistance, generally known as parasitic resistance, can reduce the overall speed of the transistor. Thus, proper LDD design must take into account the need for minimizing parasitic resistance while at the same time attenuating Em at the drain-side of the channel. Further, proper LDD design requires that the injection position associated with the maximum electric field, Em, be located under the gate conductor edge, preferably well below the silicon surface.
It is therefore desirable to produce a gate conductor which is extremely small in channel length. The small gate conductor must be one which is formed outside of the normal lithography limitations. In order to accurately produce a small gate conductor, a process must be used which avoids the limitations of lithographic exposure, develop and etch cycles applied for defining conventional gate conductors upon a gate dielectric. In order for a transistor which employs a relatively small gate conductor to achieve commercial success, improvements must be undertaken not only to the lithography procedure but also to the LDD structure itself. As Leff decreases commensurate with gate conductor size, LDD implants must be carefully controlled so as not to encroach into the relatively short channel while at the same time source/drain implants must be sufficiently concentrated to minimize HCE. Still further, the spacing of the source/drain implants must not be excessive, especially at the source-side of the channel, where parasitic resistance is most problematic.